Wednesday, February 23, 2011


Jazelle technology is found in many ARM cores. It provides hardware acceleration of managed execution environments such as Java and Microsoft Compact Framework.

Two variants of Jazelle acceleration exist:
  • Jazelle DBX (Direct Bytecode eXecution) - provides hardware execution of most Java bytecodes.
  • Jazelle RCT (Run-time Compilation Target) - provides generic extensions to accelerate AOT (ahead-of-time) and JIT (just-in-time) compilation of Java and other execution environment applications.

JTEKTM - Java Technology Enabling Kit - is a software component that can be integrated into an existing JVM (Java Virtual Machine) in order to enable Jazelle hardware acceleration.

This acceleration is completely transparent from the Java developer's point of view - no modifications are required in the application code to take advantage of the acceleration.

Tuesday, February 22, 2011


Read-Copy Update (RCU)

As an example of real-world use of RCU, consider the network routing tables. Every outgoing packet requires a check of the routing tables to determine which interface should be used. The check is fast, and, once the kernel has found the target interface, it no longer needs the routing table entry. RCU allows route lookups to be performed without locking, with significant performance benefits. The Starmode radio IP driver in the kernel also uses RCU to keep track of its list of devices. (Copy from LDD3)

Tuesday, February 15, 2011

IEEE 802.3 working group



IEEE 802.11 working group

Monday, February 14, 2011

MacBook Air

Year 0

Friday, February 11, 2011


MDIO Read Operation

MDIO Write Operation

1. MDIO Background

Thursday, February 10, 2011

DDR SDRAM (DDR1/2/3/4)

DDR 2/3 SDRAM (Double Data Rate)
ODT (On Die Termination)
Starting from DDR2, memory could have ODT in IC.
A very short introduction here.

OCD (Off-chip Driver) Calibration
A very short introduction here.

Posted CAS (Column Address Strobe) Additive Latency
CAS: A signal sent from a processor (memory controller) to a DRAM circuit to indicate that the column address lines are valid.

Uses a strobe signal (DQS) to latch data (DQ)

Strobe: One of the signals of a memory device, which is asserted to tell the memory device that the signal are valid. Upon receiving this signal the selected memory device starts the memory access (read/write). It may be driven directly by the processor (memory controller) during write and may be driven directly by the memory device during read.

DDR Comparison

Monday, February 7, 2011





1. ARM
2. Optimizing Embedded Software - A Look at the NEON SIMD unit in the ARM Cortex Family of Processors