TLB
TLB maintenance and configuration operations are controlled through CP15 coprocessor. This coprocessor provides a standard mechanism for configuring the level one memory system.
The Cortex-A9 processor implements a 2-level TLB structure. Four entries in the main TLB are lockable.
- Instruction side micro TLB
- Data side micro TLB
- Unified main TLB
Micro TLB: The first level of caching for the page table information is a micro TLB of 32 entries that is implemented on each of the instruction and data sides. These blocks provide a fully associative lookup of the virtual addresses in a single CLK signal cycle. The micro TLB returns the physical address to the cache for the address comparison, and also checks the protection attributes to signal either a Prefetch Abort or a Data Abort.
Main TLB: The main TLB catches the misses from the micro TLBs. It also provides a centralized source for lockable translation entries.
MMU
The MMU works with the L1 and L2 memory system (L1 and L2 Cache) to translate virtual addresses to physical
addresses. It also controls accesses to and from external memory.
The Virtual Memory System Architecture version 7 (VMSAv7) features include the following:
- page table entries that support 4KB, 64KB, 1MB, and 16MB
- 16 domains
- global and address space identifiers to remove the requirement for context switch TLB
flushes
- extended permissions check capability.
Example: Identity Mapping (Virtual Address = Physical Address)
Init Page Table:
init_pagetable:
ldr r2, =0b00000000000000000000110000000010
ldr r0, =PAGE_TABLE_ADDR
ldr r1, =0xfff @ loop 4096
write_descriptor:
orr r3, r2, r1, LSL #20
str r3, [r0, r1, LSL #2]
subs r1, r1, #1
bpl write_descriptor
/* Set different cacheable attributes */
@ inner write back, write allocate
@ set TEX as write back, write allocate
orr r3, r2, #1 << 20
bic r3, r3, #0b1100 @ clear CB bits
orr r3, r3, #0b0100
bic r3, r3, #0b111000000000000 @ clear TEX bits
orr r3, r3, #0b101000000000000
str r3, [r0, #0x4]
@ inner non-cacheable
@ set TEX as write back, write allocate
orr r3, r2, #2 << 20
bic r3, r3, #0b1100
orr r3, r3, #0b0000
bic r3, r3, #0b111000000000000
orr r3, r3, #0b101000000000000
str r3, [r0, #0x8]
@ inner write back, write allocate
@ outer non-cacheable
orr r3, r2, #3 << 20
bic r3, r3, #0b1100
orr r3, r3, #0b0100
bic r3, r3, #0b111000000000000
orr r3, r3, #0b100000000000000
str r3, [r0, #0xc]
@ inner non-cacheable
@ outer non-cacheable
orr r3, r2, #4 << 20
bic r3, r3, #0b1100
orr r3, r3, #0b0000
bic r3, r3, #0b111000000000000
orr r3, r3, #0b100000000000000
str r3, [r0, #0x10]
Init MMU:
@ Write Translation Table Base Control Register
mov r0, #0x0
mcr p15, 0, r0, c2, c0, 2
@ Write Translation Table Base Register 0
ldr r0, =PAGE_TABLE_ADDR
mcr p15, 0, r0, c2, c0, 0
@ Write Domain Access Control Register
@ Set Domains 0 to Client
mov r0, #0x01
mcr p15, 0, r0, c3, c0, 0
Enable MMU:
@ Read Control Register configuration data
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x1
mcr p15, 0, r0, c1, c0, 0
