System on Chip Interfaces for Low Power Design (PDF)
Paperback: 406 pages
Publisher: Morgan Kaufmann; 1 edition (December 22, 2015)
Language: English
ISBN-10: 0128016302
ISBN-13: 978-0128016305
Digital Design and Computer Architecture. ARM Edition (PDF)
Paperback: 584 pages
Publisher: Morgan Kaufmann; 1 edition (May 6, 2015)
Language: English
ISBN-10: 0128000562
ISBN-13: 978-0128000564
Showing posts with label SoC. Show all posts
Showing posts with label SoC. Show all posts
Tuesday, October 18, 2016
Tuesday, May 12, 2015
MediaTek Helio(TM) X20
MediaTek Helio(TM) X20: The World's First Mobile SoC Featuring Tri-Cluster(TM) CPU Architecture
MediaTek today announces the launch of the MediaTek Helio™ X20 -- the world's first mobile processor with Tri-Cluster™ CPU architecture and ten processing cores (Deca-core). The Helio X20 continues MediaTek's mission of delivering industry-leading computing performance coupled with unmatched power efficiency. With the integration of MediaTek's WorldMode Category 6 LTE modem with carrier aggregation and upgraded CorePilot® 3.0 advanced scheduling algorithm, the Helio X20 is set to revolutionize the mobile processor industry and address the global demand for flagship mobile devices. The Helio X20 is expected to be available in consumer products by end of this year.
Today's mobile devices are being asked to perform a wider range of tasks than ever before. Gaming requires sustained high-performance, advanced imaging and video recording need bursts of peak processor power, which are heavy load tasks. These are coupled with lighter load tasks, such as Internet browsing and audio. Battery life is also of paramount importance to all types of users. Yet existing mobile processing architectures don't efficiently meet the wide spectrum of use case scenarios. Currently, most high-end smartphones use dual cluster architectures, which limit the extent of the lowest power at one end and the computing granularity across the different configurations.
MediaTek's Tri-Cluster CPU architecture in the Helio X20 provides three processor clusters, each designed to more efficiently handle different types of workloads. The Tri-Cluster CPU consists of one cluster of two ARM Cortex-A72 cores (running at 2.5GHz for extreme performance) and two clusters of four ARM Cortex-A53 cores (one running at 2.0GHz for medium loads and one running at 1.4GHz for light activities). Much like adding gears to vehicles, dividing the cores into three clusters provides a more efficient allocation of tasks for optimum performance and extended battery life.
The Tri-Cluster CPU architecture is enabled by MediaTek's new CorePilot 3.0 heterogeneous computing scheduling algorithm. CorePilot 3.0 schedules the tasks for all CPUs and GPUs on the SoC while managing power and thermal effects so that extreme performance can be attained while creating less heat. It provides up to a 30% reduction of power consumption compared with conventional dual cluster architectures.
"By leading with mobile CPU architecture and multimedia innovation, MediaTek continues to push the envelope of power efficiency and peak performance," said Jeffrey Ju, Senior Vice President of MediaTek. "We are excited to see device manufacturers raise the bar -- in camera, display, audio and other consumer features. MediaTek has been adding innovative multimedia features to our platforms since the very beginning, enhancing the overall computing and multimedia experience as part of our strategy to put leading technology into the hands of everyone."
PR Newswire
MediaTek today announces the launch of the MediaTek Helio™ X20 -- the world's first mobile processor with Tri-Cluster™ CPU architecture and ten processing cores (Deca-core). The Helio X20 continues MediaTek's mission of delivering industry-leading computing performance coupled with unmatched power efficiency. With the integration of MediaTek's WorldMode Category 6 LTE modem with carrier aggregation and upgraded CorePilot® 3.0 advanced scheduling algorithm, the Helio X20 is set to revolutionize the mobile processor industry and address the global demand for flagship mobile devices. The Helio X20 is expected to be available in consumer products by end of this year.
Today's mobile devices are being asked to perform a wider range of tasks than ever before. Gaming requires sustained high-performance, advanced imaging and video recording need bursts of peak processor power, which are heavy load tasks. These are coupled with lighter load tasks, such as Internet browsing and audio. Battery life is also of paramount importance to all types of users. Yet existing mobile processing architectures don't efficiently meet the wide spectrum of use case scenarios. Currently, most high-end smartphones use dual cluster architectures, which limit the extent of the lowest power at one end and the computing granularity across the different configurations.
MediaTek's Tri-Cluster CPU architecture in the Helio X20 provides three processor clusters, each designed to more efficiently handle different types of workloads. The Tri-Cluster CPU consists of one cluster of two ARM Cortex-A72 cores (running at 2.5GHz for extreme performance) and two clusters of four ARM Cortex-A53 cores (one running at 2.0GHz for medium loads and one running at 1.4GHz for light activities). Much like adding gears to vehicles, dividing the cores into three clusters provides a more efficient allocation of tasks for optimum performance and extended battery life.
The Tri-Cluster CPU architecture is enabled by MediaTek's new CorePilot 3.0 heterogeneous computing scheduling algorithm. CorePilot 3.0 schedules the tasks for all CPUs and GPUs on the SoC while managing power and thermal effects so that extreme performance can be attained while creating less heat. It provides up to a 30% reduction of power consumption compared with conventional dual cluster architectures.
"By leading with mobile CPU architecture and multimedia innovation, MediaTek continues to push the envelope of power efficiency and peak performance," said Jeffrey Ju, Senior Vice President of MediaTek. "We are excited to see device manufacturers raise the bar -- in camera, display, audio and other consumer features. MediaTek has been adding innovative multimedia features to our platforms since the very beginning, enhancing the overall computing and multimedia experience as part of our strategy to put leading technology into the hands of everyone."
PR Newswire
Wednesday, April 9, 2014
Monday, January 27, 2014
[Book] Multicore
Smart Multicore Embedded Systems (PDF)
Massimo Torquati, Koen Bertels, Sven Karlsson
214 pages
Publisher: Springer; 2014 edition (November 26, 2013)
ISBN-10: 1461487994
ISBN-13: 978-1461487999
How to get more performance on multi-core system?
From hardware point of view
From software point of view
Multicore Computing: Algorithms, Architectures, and Applications
Massimo Torquati, Koen Bertels, Sven Karlsson
214 pages
Publisher: Springer; 2014 edition (November 26, 2013)
ISBN-10: 1461487994
ISBN-13: 978-1461487999
How to get more performance on multi-core system?
Multi-thread program
Multicore Computing: Algorithms, Architectures, and Applications
Editor(s):Sanguthevar Rajasekaran, Lance Fiondella, Mohamed Ahmed, Reda A. Ammar
452 Pages
Published: December 12, 2013 by Chapman and Hall/CRC
Tuesday, November 27, 2012
Benchmark CPU performance
Build CoreMark
For x86 platform:
[ ] # make compile XCFLAGS="-g -DMULTITHREAD=8 -DUSE_FORK=1 -DPERFORMANCE_RUN=1"
[ ] # make compile XCFLAGS="-g -DMULTITHREAD=4 -DUSE_FORK=1 -DPERFORMANCE_RUN=1"
[ ] # make compile XCFLAGS="-g -DPERFORMANCE_RUN=1"
For ARM platform:
[ ] # make compile CC=arm-linux-gcc XCFLAGS="-g -DPERFORMANCE_RUN=1"
Execute CoreMark
[ ]# ./coremark.exe 0x0 0x0 0x66 0 7 1 2000
Sketch the scores
Data format in "coremark.gnuplot_x86.data"
1 7526.256372
2 15053.542714
3 16116.625765
4 20295.202952
[ ] # gnuplot
set xlabel "Core"
set ylabel "Iterations/Sec"
set xzeroaxis
set yzeroaxis
set xrange [0:5]
set yrange [0:30000]
set term png size 600, 400
set title "CoreMark with different x86 core number"
set output "x86-MP.CoreMark.png"
plot "coremark.gnuplot_x86.data" using 1:2 title "4 Processes" with linespoint
Other Example:
gnuplot> plot "coremark.gnuplot_x86.data" using 1:2 title "1 Process" with linespoint, "coremark.gnuplot.data" using 1:3 title "4 Processes" with linespoint, "coremark.gnuplot.data" using 1:4 title "8 Processes" with linespoint
Other Benchmark Tools:
Linpack
Quadrant
Geekbench 2
Vellamo
Andebench
Antutu Benchmark-59
Caffeine mark (example)
Nbench
GLBenchmark 2.1.4-10
Reference:
Tegra II vs. TI OMAP PandaBoard
For x86 platform:
[ ] # make compile XCFLAGS="-g -DMULTITHREAD=8 -DUSE_FORK=1 -DPERFORMANCE_RUN=1"
[ ] # make compile XCFLAGS="-g -DMULTITHREAD=4 -DUSE_FORK=1 -DPERFORMANCE_RUN=1"
[ ] # make compile XCFLAGS="-g -DPERFORMANCE_RUN=1"
For ARM platform:
[ ] # make compile CC=arm-linux-gcc XCFLAGS="-g -DPERFORMANCE_RUN=1"
Execute CoreMark
[ ]# ./coremark.exe 0x0 0x0 0x66 0 7 1 2000
Sketch the scores
Data format in "coremark.gnuplot_x86.data"
1 7526.256372
2 15053.542714
3 16116.625765
4 20295.202952
[ ] # gnuplot
set xlabel "Core"
set ylabel "Iterations/Sec"
set xzeroaxis
set yzeroaxis
set xrange [0:5]
set yrange [0:30000]
set term png size 600, 400
set title "CoreMark with different x86 core number"
set output "x86-MP.CoreMark.png"
plot "coremark.gnuplot_x86.data" using 1:2 title "4 Processes" with linespoint
Other Example:
gnuplot> plot "coremark.gnuplot_x86.data" using 1:2 title "1 Process" with linespoint, "coremark.gnuplot.data" using 1:3 title "4 Processes" with linespoint, "coremark.gnuplot.data" using 1:4 title "8 Processes" with linespoint
Other Benchmark Tools:
Reference:
Tegra II vs. TI OMAP PandaBoard
Friday, March 18, 2011
HOWTO install OpenOCD in Fedora 14
Compile OpenOCD
[ ]# mkdir /home/OpenOCD
[ ]# cd /home/OpenOCD
Download FT2xxx USB-UART drivers from FTDI Ltd
[ ]# wget http://www.ftdichip.com/Drivers/D2XX/Linux/libftd2xx0.4.16.tar.gz
[ ]# tar zxvf libftd2xx0.4.16.tar.gz
[ ]# cd libftd2xx0.4.16
[ ]# cp ftd2xx.h WinTypes.h /usr/include/
[ ]# cp libftd2xx.so.0.4.16 /usr/lib/libftd2xx.so.0.4.16
[ ]# ln -sf /usr/lib/libftd2xx.so.0.4.16 /usr/lib/libftd2xx.so.0.4
[ ]# ln -sf /usr/lib/libftd2xx.so.0.4.16 /usr/lib/libftd2xx.so.0
[ ]# ln -sf /usr/lib/libftd2xx.so.0.4.16 /usr/lib/libftd2xx.so
Download/Compile latest OpenOCD from GIT:
[ ]# cd /home/OpenOCD
[ ]# git clone git://openocd.git.sourceforge.net/gitroot/openocd/openocd
[ ]# cd openocd
[ ]# ./bootstrap
[ ]# ./configure --enable-maintainer-mode --enable-ft2232_ftd2xx
[ ]# make
[ ]# make install
Or Download/Compile OpenOCD 4.0 tarball
[ ]# wget http://download.berlios.de/openocd/openocd-0.4.0.tar.bz2
[ ]# tar jxvf openocd-0.4.0.tar.bz2
[ ]# cd openocd-0.4.0
[ ]# ./configure --enable-maintainer-mode --enable-ft2232_ftd2xx
[ ]# make
[ ]# make install
What OpenOCD can do for a developer
1. Read/Write register on your target
2. Read/Write memory on your target
3. Program flash chips
4. GDB
5. more...
How to use OpenOCD
[ ]# mkdir /home/OpenOCD
[ ]# cd /home/OpenOCD
Download FT2xxx USB-UART drivers from FTDI Ltd
[ ]# wget http://www.ftdichip.com/Drivers/D2XX/Linux/libftd2xx0.4.16.tar.gz
[ ]# tar zxvf libftd2xx0.4.16.tar.gz
[ ]# cd libftd2xx0.4.16
[ ]# cp ftd2xx.h WinTypes.h /usr/include/
[ ]# cp libftd2xx.so.0.4.16 /usr/lib/libftd2xx.so.0.4.16
[ ]# ln -sf /usr/lib/libftd2xx.so.0.4.16 /usr/lib/libftd2xx.so.0.4
[ ]# ln -sf /usr/lib/libftd2xx.so.0.4.16 /usr/lib/libftd2xx.so.0
[ ]# ln -sf /usr/lib/libftd2xx.so.0.4.16 /usr/lib/libftd2xx.so
Download/Compile latest OpenOCD from GIT:
[ ]# cd /home/OpenOCD
[ ]# git clone git://openocd.git.sourceforge.net/gitroot/openocd/openocd
[ ]# cd openocd
[ ]# ./bootstrap
[ ]# ./configure --enable-maintainer-mode --enable-ft2232_ftd2xx
[ ]# make
[ ]# make install
Or Download/Compile OpenOCD 4.0 tarball
[ ]# wget http://download.berlios.de/openocd/openocd-0.4.0.tar.bz2
[ ]# tar jxvf openocd-0.4.0.tar.bz2
[ ]# cd openocd-0.4.0
[ ]# ./configure --enable-maintainer-mode --enable-ft2232_ftd2xx
[ ]# make
[ ]# make install
What OpenOCD can do for a developer
1. Read/Write register on your target
2. Read/Write memory on your target
3. Program flash chips
4. GDB
5. more...
How to use OpenOCD
Running OpenOCD on Cavium Networks CNS3000/CNW5000 Platform
[ ]# ./openocd -f openocd-cnx.cfgOpen On-Chip Debugger 0.4.0 (2011-03-22-03:04)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
6000 kHz
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
jtag_ntrst_delay: 100
jtag_nsrst_delay: 100
Info : device: 4 "2232C"
Info : deviceID: 341266712
Info : SerialNumber:
Info : Description: USB<=>JTAG&RS232 A
Info : clock speed 6000 kHz
Info : JTAG tap: arm11.cpu tap/device found: 0x07b37477 (mfg: 0x23b, part: 0x7b37, ver: 0x0)
Info : JTAG tap: arm11.cpu tap/device found: 0x07b37477 (mfg: 0x23b, part: 0x7b37, ver: 0x0)
Warn : JTAG tap: arm11.cpu UNEXPECTED: 0x07b37477 (mfg: 0x23b, part: 0x7b37, ver: 0x0)
Error: JTAG tap: arm11.cpu expected 1 of 1: 0xffffffff (mfg: 0x7ff, part: 0xffff, ver: 0xf)
Error: Trying to use configured scan chain anyway...
Warn : Bypassing JTAG setup events due to errors
Info : found ARM11 MPCore
Info : arm11.cpu: hardware has 6 breakpoints, 2 watchpoints
Info : accepting 'telnet' connection from 0
Recover u-boot
[ ]# telnet localhost 4444
> halt
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x600001d3 pc: 0x000146c4
> flash probe 0
Flash Manufacturer/Device: 0x0001 0x227e
configuration specifies 0x800000 size, but a 0x1000000 size flash was found
flash 'cfi' found at 0x10000000
> flash list
{name cfi base 268435456 size 8388608 bus_width 2 chip_width 2}
> flash info 0
#0 : cfi at 0x10000000, size 0x00800000, buswidth 2, chipwidth 2
# 0: 0x00000000 (0x20000 128kB) protection state unknown
# 1: 0x00020000 (0x20000 128kB) protection state unknown
# 2: 0x00040000 (0x20000 128kB) protection state unknown
. . .
#125: 0x00fa0000 (0x20000 128kB) protection state unknown
#126: 0x00fc0000 (0x20000 128kB) protection state unknown
#127: 0x00fe0000 (0x20000 128kB) protection state unknown
cfi information:
mfr: 0x0001, id:0x227e
qry: 'QRY', pri_id: 0x0002, pri_addr: 0x0040, alt_id: 0x0000, alt_addr: 0x0000
Vcc min: 2.7, Vcc max: 3.6, Vpp min: 0.0, Vpp max: 0.0
typ. word write timeout: 64, typ. buf write timeout: 64, typ. block erase timeout: 512, typ. chip erase timeout: 524288
max. word write timeout: 512, max. buf write timeout: 2048, max. block erase timeout: 4096, max. chip erase timeout: 2097152
size: 0x1000000, interface desc: 2, max buffer write size: 40
Spansion primary algorithm extend information:
pri: 'PRI', version: 1.3
Silicon Rev.: 0x5, Address Sensitive unlock: 0x0
Erase Suspend: 0x2, Sector Protect: 0x1
VppMin: 11.5, VppMax: 12.5
> flash erase_address 0x10000000 0x40000
erased address 0x10000000 (length 262144) in 1.737926s (147.302 kb/s)
> flash write_bank 0 /tftpboot/u-boot.bin 0
No working memory available. Specify -work-area-phys to target.
Programming at 10000000, count 000295d8 bytes remaining
Programming at 10000100, count 000294d8 bytes remaining
. . .
Programming at 10029300, count 000002d8 bytes remaining
Programming at 10029400, count 000001d8 bytes remaining
Programming at 10029500, count 000000d8 bytes remaining
wrote 169432 bytes from file /tftpboot/u-boot.bin to flash bank 0 at offset 0x00000000 in 810.315613s (0.204 kb/s)
> reset
> halt
> arm disassemble 0x10000000
core state: ARM
0x00989680 0xfdfefbfd LDC2L p11, c15, [r14, #244]!
0x10000000 0xea000013 B 0x10000054
0x10000004 0xe59ff014 LDR r15, [r15, #0x14]
0x10000008 0xe59ff014 LDR r15, [r15, #0x14]
0x10000000 0xea000013 B 0x10000054
0x10000004 0xe59ff014 LDR r15, [r15, #0x14]
0x10000008 0xe59ff014 LDR r15, [r15, #0x14]
0x1000000c 0xe59ff014 LDR r15, [r15, #0x14]
0x10000010 0xe59ff014 LDR r15, [r15, #0x14]
0x10000014 0xe59ff014 LDR r15, [r15, #0x14]
0x10000018 0xe59ff014 LDR r15, [r15, #0x14]
0x1000001c 0xe59ff014 LDR r15, [r15, #0x14]
0x10000020 0x00000120 ANDEQ r0, r0, r0, LSR #0x2
0x10000024 0x00000180 ANDEQ r0, r0, r0, LSL #0x3
0x10000028 0x000001e0 ANDEQ r0, r0, r0, ROR #0x3
0x1000002c 0x00000240 ANDEQ r0, r0, r0, ASR #0x4
0x10000030 0x000002a0 ANDEQ r0, r0, r0, LSR #0x5
0x10000034 0x00000300 ANDEQ r0, r0, r0, LSL #0x6
0x10000038 0x00000360 ANDEQ r0, r0, r0, ROR #0x6
0x1000003c 0xdeadbeef CDPLE p14, 0x0a, c11, c13, c15, 0x07
0x10000040 0x00000000 ANDEQ r0, r0, r0
0x10000044 0x00000000 ANDEQ r0, r0, r0
0x10000048 0x08000000 STMDAEQ r0, i??i??i}
0x1000004c 0x000295d8 LDREQD r9, [r2], -r8
0x10000050 0x00071600 ANDEQ r1, r7, r0, LSL #0xc
0x10000054 0xe10f0000 MRS r0, CPSR
0x10000058 0xe3c0001f BIC r0, r0, #0x1f
0x1000005c 0xe38000d3 ORR r0, r0, #0xd3
...
Here is what I used to try -- [$800 NT, $30 USD]
OpenJTAG ARM JTAG USB
TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0* arm11.cpu arm11 little arm11.cpu halted
Recover u-boot
[ ]# telnet localhost 4444
> halt
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x600001d3 pc: 0x000146c4
> flash probe 0
Flash Manufacturer/Device: 0x0001 0x227e
configuration specifies 0x800000 size, but a 0x1000000 size flash was found
flash 'cfi' found at 0x10000000
> flash list
{name cfi base 268435456 size 8388608 bus_width 2 chip_width 2}
> flash info 0
#0 : cfi at 0x10000000, size 0x00800000, buswidth 2, chipwidth 2
# 0: 0x00000000 (0x20000 128kB) protection state unknown
# 1: 0x00020000 (0x20000 128kB) protection state unknown
# 2: 0x00040000 (0x20000 128kB) protection state unknown
. . .
#125: 0x00fa0000 (0x20000 128kB) protection state unknown
#126: 0x00fc0000 (0x20000 128kB) protection state unknown
#127: 0x00fe0000 (0x20000 128kB) protection state unknown
cfi information:
mfr: 0x0001, id:0x227e
qry: 'QRY', pri_id: 0x0002, pri_addr: 0x0040, alt_id: 0x0000, alt_addr: 0x0000
Vcc min: 2.7, Vcc max: 3.6, Vpp min: 0.0, Vpp max: 0.0
typ. word write timeout: 64, typ. buf write timeout: 64, typ. block erase timeout: 512, typ. chip erase timeout: 524288
max. word write timeout: 512, max. buf write timeout: 2048, max. block erase timeout: 4096, max. chip erase timeout: 2097152
size: 0x1000000, interface desc: 2, max buffer write size: 40
Spansion primary algorithm extend information:
pri: 'PRI', version: 1.3
Silicon Rev.: 0x5, Address Sensitive unlock: 0x0
Erase Suspend: 0x2, Sector Protect: 0x1
VppMin: 11.5, VppMax: 12.5
> flash erase_address 0x10000000 0x40000
erased address 0x10000000 (length 262144) in 1.737926s (147.302 kb/s)
> flash write_bank 0 /tftpboot/u-boot.bin 0
No working memory available. Specify -work-area-phys to target.
Programming at 10000000, count 000295d8 bytes remaining
Programming at 10000100, count 000294d8 bytes remaining
. . .
Programming at 10029300, count 000002d8 bytes remaining
Programming at 10029400, count 000001d8 bytes remaining
Programming at 10029500, count 000000d8 bytes remaining
wrote 169432 bytes from file /tftpboot/u-boot.bin to flash bank 0 at offset 0x00000000 in 810.315613s (0.204 kb/s)
> reset
Disassemble u-boot
[ ]# telnet localhost 4444> halt
> arm disassemble 0x10000000
core state: ARM
0x00989680 0xfdfefbfd LDC2L p11, c15, [r14, #244]!
0x10000000 0xea000013 B 0x10000054
0x10000004 0xe59ff014 LDR r15, [r15, #0x14]
0x10000008 0xe59ff014 LDR r15, [r15, #0x14]
0x10000000 0xea000013 B 0x10000054
0x10000004 0xe59ff014 LDR r15, [r15, #0x14]
0x10000008 0xe59ff014 LDR r15, [r15, #0x14]
0x1000000c 0xe59ff014 LDR r15, [r15, #0x14]
0x10000010 0xe59ff014 LDR r15, [r15, #0x14]
0x10000014 0xe59ff014 LDR r15, [r15, #0x14]
0x10000018 0xe59ff014 LDR r15, [r15, #0x14]
0x1000001c 0xe59ff014 LDR r15, [r15, #0x14]
0x10000020 0x00000120 ANDEQ r0, r0, r0, LSR #0x2
0x10000024 0x00000180 ANDEQ r0, r0, r0, LSL #0x3
0x10000028 0x000001e0 ANDEQ r0, r0, r0, ROR #0x3
0x1000002c 0x00000240 ANDEQ r0, r0, r0, ASR #0x4
0x10000030 0x000002a0 ANDEQ r0, r0, r0, LSR #0x5
0x10000034 0x00000300 ANDEQ r0, r0, r0, LSL #0x6
0x10000038 0x00000360 ANDEQ r0, r0, r0, ROR #0x6
0x1000003c 0xdeadbeef CDPLE p14, 0x0a, c11, c13, c15, 0x07
0x10000040 0x00000000 ANDEQ r0, r0, r0
0x10000044 0x00000000 ANDEQ r0, r0, r0
0x10000048 0x08000000 STMDAEQ r0, i??i??i}
0x1000004c 0x000295d8 LDREQD r9, [r2], -r8
0x10000050 0x00071600 ANDEQ r1, r7, r0, LSL #0xc
0x10000054 0xe10f0000 MRS r0, CPSR
0x10000058 0xe3c0001f BIC r0, r0, #0x1f
0x1000005c 0xe38000d3 ORR r0, r0, #0xd3
...
Here is what I used to try -- [$800 NT, $30 USD]
OpenJTAG ARM JTAG USB
The man page for ARM11 CPU
(Download)Friday, March 4, 2011
Thursday, February 10, 2011
DDR SDRAM (DDR1/2/3/4)
DDR 2/3 SDRAM (Double Data Rate)
Starting from DDR2, memory could have ODT in IC.
A very short introduction here.
OCD (Off-chip Driver) Calibration
A very short introduction here.
Posted CAS (Column Address Strobe) Additive Latency
CAS: A signal sent from a processor (memory controller) to a DRAM circuit to indicate that the column address lines are valid.
DQ/DQS
Uses a strobe signal (DQS) to latch data (DQ)
Strobe: One of the signals of a memory device, which is asserted to tell the memory device that the signal are valid. Upon receiving this signal the selected memory device starts the memory access (read/write). It may be driven directly by the processor (memory controller) during write and may be driven directly by the memory device during read.
DDR Comparison
Monday, May 3, 2010
I2C Bus
I2C
I2C Linux Device Driver
The major driver is composed of the following:
I2C Test Tools on Linux
i2c-tools
eeprog
Reference:
I2C Linux Device Driver
- Adapter specific code: /drivers/i2c/busses/i2c-xxxx.c
- Algorithm: /drivers/i2c/algos/i2c-algo-xxxx.c
- I2C-core: /drivers/i2c/i2c-core.c
- I2C-dev: /drivers/i2c/i2c-dev.c The I2C-dev block allows the userland program to access the I2C device (ex, EEPROM, RTC) through the /dev interface.
I2C Test Tools on Linux
i2c-tools
eeprog
Reference:
Monday, April 27, 2009
Thursday, April 23, 2009
MMC/SD on u-boot
Card Information
Load bootpImage from MMC/SD Card
u-boot # mmcinfo
mmc_init
version_2 = 1
Manufacturer ID: 03
OEM/Application ID: 5344
Product name: SD08G
Product Revision: 8.0
Product Serial Number: 59007
Manufacturing Date: 08/12
MMC/SD RCA = 0x8FE4
CSD data: 400e0032 5b590000 3cdc7f80 0a404000
CSD structure version: 1
Card command classes: 5b5
Read block length: 512
Does not support partial reads
Write block length: 512
Does not support partial writes
Does not support group WP
Card capacity: 7977472 Kbytes
File format: 0/0
Write protection:
u-boot # fatinfo mmc 0
Interface: MMC
Device 0: Vendor: Man 035344 Snr 0000e67f Rev: 8 0 Prod: SD08G
Type: Removable Hard Disk
Capacity: 7790.5 MB = 7.6 GB (15954944 x 512)
Partition 1: Filesystem: FAT32 "NO NAME "
u-boot # fatls mmc 0
3745704 bootpimage
1 file(s), 0 dir(s)
u-boot # fatload mmc 0 0x1000000 bootpImage
reading bootpImage
3745704 bytes read
u-boot # go 0x1000000
Download Patch
Reference:
1. Simplified Physical Layer Spec. (Version 2.00)
2. Simplified SD Host Controller Spec. (Version 2.00)
3. Simplified SDIO Card Spec. (Version 2.00)
Load bootpImage from MMC/SD Card
u-boot # mmcinfo
mmc_init
version_2 = 1
Manufacturer ID: 03
OEM/Application ID: 5344
Product name: SD08G
Product Revision: 8.0
Product Serial Number: 59007
Manufacturing Date: 08/12
MMC/SD RCA = 0x8FE4
CSD data: 400e0032 5b590000 3cdc7f80 0a404000
CSD structure version: 1
Card command classes: 5b5
Read block length: 512
Does not support partial reads
Write block length: 512
Does not support partial writes
Does not support group WP
Card capacity: 7977472 Kbytes
File format: 0/0
Write protection:
u-boot # fatinfo mmc 0
Interface: MMC
Device 0: Vendor: Man 035344 Snr 0000e67f Rev: 8 0 Prod: SD08G
Type: Removable Hard Disk
Capacity: 7790.5 MB = 7.6 GB (15954944 x 512)
Partition 1: Filesystem: FAT32 "NO NAME "
u-boot # fatls mmc 0
3745704 bootpimage
1 file(s), 0 dir(s)
u-boot # fatload mmc 0 0x1000000 bootpImage
reading bootpImage
3745704 bytes read
u-boot # go 0x1000000
Download Patch
Reference:
1. Simplified Physical Layer Spec. (Version 2.00)
2. Simplified SD Host Controller Spec. (Version 2.00)
3. Simplified SDIO Card Spec. (Version 2.00)
Friday, January 16, 2009
DMA Controller
DMA
DMA Read Operation:
1. DMAC transfers the data from the I/O device into the main memory.
2. DMAC issues an interrupt to the CPU signaling the reception of data.
3. CPU accesses the main memory and processes the received data
DMA Write Operation:
1. CPU writes the data into the main memory.
2. CPU signals the DMAC to start the transaction.
3. DMAC transfers the data from the main memory into the I/O device.
Two important properties of memory systems
Coherence and Consistency
Coherence concerns only one memory location
Consistency concerns apparent ordering for all locations
Coherence defines the behavior of reads and writes to the same memory location.
Consistency defines the behavior of reads and writes with respect to accesses to other memory locations.
DMA Read Operation:
1. DMAC transfers the data from the I/O device into the main memory.
2. DMAC issues an interrupt to the CPU signaling the reception of data.
3. CPU accesses the main memory and processes the received data
DMA Write Operation:
1. CPU writes the data into the main memory.
2. CPU signals the DMAC to start the transaction.
3. DMAC transfers the data from the main memory into the I/O device.
Two important properties of memory systems
Coherence and Consistency
Coherence concerns only one memory location
Consistency concerns apparent ordering for all locations
Coherence defines the behavior of reads and writes to the same memory location.
Consistency defines the behavior of reads and writes with respect to accesses to other memory locations.
Wednesday, December 17, 2008
JTAG
Parallel JTAG Cable
1. How To Do Jtag Cable
2. Benjamin Henrion Web Space
USB JTAG Cable
1. Gateworks USB JTAG Programmer
2. USB JTAG adapter
3. Bus_Blaster
Here is the thing that I would like to program on-board flash in embedded device. Is it possible to use this cable and a programming utility running on a Windows/Linux PC enables me to do this?
Wiggler JTAG Cable
This kind of cable is the most simple one and can be make by yourself. Check Benjamin Henrion's Web Space for more information. You can also buy one from OLIMEX or TechToys.
How to use the JTAG flash utility
H-JTAG - a free JTAG debug agent for ARM
JTAG Tools -
UrJTAG - Universal JTAG library, server and tools
PortTalk - A Windows NT I/O Port Device Driver
Amontec JTAGkey -
JTAGER -
Reference:
Wiki
fpga4fun
Here is what I used to try -- $800 NT
OpenJTAG ARM JTAG USB
1. How To Do Jtag Cable
2. Benjamin Henrion Web Space
USB JTAG Cable
1. Gateworks USB JTAG Programmer
2. USB JTAG adapter
3. Bus_Blaster
Here is the thing that I would like to program on-board flash in embedded device. Is it possible to use this cable and a programming utility running on a Windows/Linux PC enables me to do this?
Wiggler JTAG Cable
This kind of cable is the most simple one and can be make by yourself. Check Benjamin Henrion's Web Space for more information. You can also buy one from OLIMEX or TechToys.
How to use the JTAG flash utility
H-JTAG - a free JTAG debug agent for ARM
JTAG Tools -
UrJTAG - Universal JTAG library, server and tools
PortTalk - A Windows NT I/O Port Device Driver
Amontec JTAGkey -
JTAGER -
Reference:
Wiki
fpga4fun
Here is what I used to try -- $800 NT
OpenJTAG ARM JTAG USB
Monday, November 24, 2008
Serial Interface
SPI (Serial Peripheral Interface)
wiki
serial-peripheral-interface-spi
I2C (Inter-IC)
I2C Specification 2.1 (PDF)
I2S (Inter-IC Sound)
I2S Specification (PDF)
JTAG (Joint Test Action Group)
JTAG Boundary Scan 1149.1 Specification Standard
Interduction to JTAG
wiki
serial-peripheral-interface-spi
I2C (Inter-IC)
I2C Specification 2.1 (PDF)
I2S (Inter-IC Sound)
I2S Specification (PDF)
JTAG (Joint Test Action Group)
JTAG Boundary Scan 1149.1 Specification Standard
Interduction to JTAG
Tuesday, October 28, 2008
Open On-Chip Debugger
Open On-Chip Debugger
Openocd - JTAG Interface
Setting Up OpenOCD Under Linux
The USB ARM JTAG programmers. (Compliant with OpenOCD)
These are based on the FTDI USB chip.
Hubert Hoegl's USB ARM JTAG Programmer
USB JTAG-Programmer
OpenOCD website
Sparkfun
Olimex
Related Blogs:
JTAG Cable
Openocd - JTAG Interface
Setting Up OpenOCD Under Linux
The USB ARM JTAG programmers. (Compliant with OpenOCD)
These are based on the FTDI USB chip.
Hubert Hoegl's USB ARM JTAG Programmer
USB JTAG-Programmer
OpenOCD website
Sparkfun
Olimex
Related Blogs:
JTAG Cable
Tuesday, September 23, 2008
SoC Bus
AMBA
AMBA 1.0
1. ASB (Advanced System Bus)
2. APB (Advanced Peripheral Bus)
AMBA 2.0
1. AHB (Advanced High-performance Bus)
2. ASB
3. APB (Advanced Peripheral Bus)
AMBA 3.0
1. AXI (Advanced eXtensible Interface)
2. APB
3. AHB-lite
4. ATB (Advanced Trace Bus)
CoreConnect
1. PLB (Processor Local Bus)
2. OPB (On-chip Peripheral Bus)
3. DCR (Device Control Register)
OCP (Open Core Protocol)
Wishbone
Reference:
Introduction to AMBA Bus System (Chinese)
ARM AMBA Overview
AMBA 1.0
1. ASB (Advanced System Bus)
2. APB (Advanced Peripheral Bus)
AMBA 2.0
1. AHB (Advanced High-performance Bus)
2. ASB
3. APB (Advanced Peripheral Bus)
AMBA 3.0
1. AXI (Advanced eXtensible Interface)
2. APB
3. AHB-lite
4. ATB (Advanced Trace Bus)
CoreConnect
1. PLB (Processor Local Bus)
2. OPB (On-chip Peripheral Bus)
3. DCR (Device Control Register)
OCP (Open Core Protocol)
Wishbone
Reference:
Introduction to AMBA Bus System (Chinese)
ARM AMBA Overview
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