The 2 Good Books

System on Chip Interfaces for Low Power Design (PDF)

Paperback: 406 pages
Publisher: Morgan Kaufmann; 1 edition (December 22, 2015)
Language: English
ISBN-10: 0128016302
ISBN-13: 978-0128016305

Digital Design and Computer Architecture. ARM Edition (PDF)

Paperback: 584 pages
Publisher: Morgan Kaufmann; 1 edition (May 6, 2015)
Language: English
ISBN-10: 0128000562
ISBN-13: 978-0128000564

Cortex-M on Mac OS

Build Toolchain

• Xcode
• Install MacTex
• Prepare source tarball 

Copy the src release package into ~/mac-build/ directory
$ cp gcc-arm-none-eabi-5_3-2016q1-20160330-src.tar.bz2 ~/mac-build 

Prepare source codes
$ cd ~/mac-build
$ tar xjf gcc-arm-none-eabi-5_3-2016q1-20160330-src.tar.bz2
$ cd ./gcc-arm-none-eabi-5_3-2016q1-20160330/src
$ find . -name '*.tar.*' | xargs -I% tar -xf %
$ cd ..

• Build the toolchain

Start building the toolchain.
$ ./build-prerequisites.sh
$ ./build-toolchain.sh

Cortex-M Platform

[TTBD] TI, NXP, ?

MediaTek Helio(TM) X20

MediaTek Helio(TM) X20: The World's First Mobile SoC Featuring Tri-Cluster(TM) CPU Architecture


MediaTek today announces the launch of the MediaTek Helio™ X20 -- the world's first mobile processor with Tri-Cluster™ CPU architecture and ten processing cores (Deca-core). The Helio X20 continues MediaTek's mission of delivering industry-leading computing performance coupled with unmatched power efficiency. With the integration of MediaTek's WorldMode Category 6 LTE modem with carrier aggregation and upgraded CorePilot® 3.0 advanced scheduling algorithm, the Helio X20 is set to revolutionize the mobile processor industry and address the global demand for flagship mobile devices. The Helio X20 is expected to be available in consumer products by end of this year. 

Today's mobile devices are being asked to perform a wider range of tasks than ever before. Gaming requires sustained high-performance, advanced imaging and video recording need bursts of peak processor power, which are heavy load tasks. These are coupled with lighter load tasks, such as Internet browsing and audio. Battery life is also of paramount importance to all types of users. Yet existing mobile processing architectures don't efficiently meet the wide spectrum of use case scenarios. Currently, most high-end smartphones use dual cluster architectures, which limit the extent of the lowest power at one end and the computing granularity across the different configurations. 

MediaTek's Tri-Cluster CPU architecture in the Helio X20 provides three processor clusters, each designed to more efficiently handle different types of workloads. The Tri-Cluster CPU consists of one cluster of two ARM Cortex-A72 cores (running at 2.5GHz for extreme performance) and two clusters of four ARM Cortex-A53 cores (one running at 2.0GHz for medium loads and one running at 1.4GHz for light activities). Much like adding gears to vehicles, dividing the cores into three clusters provides a more efficient allocation of tasks for optimum performance and extended battery life. 

The Tri-Cluster CPU architecture is enabled by MediaTek's new CorePilot 3.0 heterogeneous computing scheduling algorithm. CorePilot 3.0 schedules the tasks for all CPUs and GPUs on the SoC while managing power and thermal effects so that extreme performance can be attained while creating less heat. It provides up to a 30% reduction of power consumption compared with conventional dual cluster architectures. 

 "By leading with mobile CPU architecture and multimedia innovation, MediaTek continues to push the envelope of power efficiency and peak performance," said Jeffrey Ju, Senior Vice President of MediaTek. "We are excited to see device manufacturers raise the bar -- in camera, display, audio and other consumer features. MediaTek has been adding innovative multimedia features to our platforms since the very beginning, enhancing the overall computing and multimedia experience as part of our strategy to put leading technology into the hands of everyone."

PR Newswire

Juno ARM Development Platform

Juno

CPU: ARM® Cortex®-A57 and Cortex-A53 MPCore for ARMv8 big.LITTLE™

• 2x ARM Cortex A57 cores @ 1.1 GHz (2MB L2 cache) 
• 4x ARM Cortex A53 cores @ 850 MHz (1MB L2 cache)

GPU: Mali™-T624 for 3D Graphics Acceleration and GP-GPU compute (@ 600 MHz)
        
System Control Processor (SCP): ARMv7-M

Software SDK

LDK
Android

ARM Cortex-M

ARM Corex-M3

SoC


Toolchain

Sourcery CodeBench Lite releases for ARM EABI, ARM GNU/Linux, ARM AARCH64-Linux, IA32/IA64 GNU/Linux and ELF are no longer available. :(

Thanks to http://www.carlson-minot.com/ (For Mac OS X User)

Boot Code




Book

Assembly Language Programming: ARM Cortex-M3 (PDF)

Vincent Mahout


Wiley-ISTE
ISBN: 978-1-84821-329-6

February 2012
256 pages

Exynos 5420 Arndale Octa Board

Copy from http://www.pyrustek.com

7 inch LCD Panel with Touch and LVDS interface

MIPI-DSI 4 Lane and eDP interface
7 Inch TFT LCD, Resolution 1024 * 600
Capacitive Touchscreen

Hardware: TC358764/5 Display Bridge (MIPI-DSI to LVDS)

Software:

SABRE Lite I.MX6 Development Board

Development Board

LCD8000-97C：9.7" LCD Module

Cortex A15 Development Kit

TI
OMAP5432 EVM

Samsung
Exynos 5250 Arndale Board
Exynos 5420 Arndale Octa Board
   http://www.arndaleboard.org/wiki/index.php/O_WiKi

Exynos5 Octa ODROID-XU+E
   http://odroid.com/dokuwiki

CodeBench ARM Cross-Compiler on Mac OS X

1. Install MacTex
    http://mirror.ctan.org/systems/mac/mactex/MacTeX.pkg
2. Install GNU sed, awk
    $ brew install sed
    $ brew install gawk
3. Install gettext
    http://ftp.gnu.org/pub/gnu/gettext/gettext-0.18.3.2.tar.gz
 
    $ cd gettext-0.18.3.2
    $ ./configure
    $ make
    $ sudo make install

4. CodeBench Lite
    https://sourcery.mentor.com/GNUToolchain/release2642
5. Build
    patch -
    script -

No kidding, I take one day to compile the ARM toolchain.

Hitachi OPV5XC SoC

http://www.hitachi.com/products/it/network/soc/

[Book] Professional Embedded ARM Development

Professional Embedded ARM Development (PDF)

James A. Langbridge

Published: December 2013 by Wiley
ISBN: 978-1-118-78894-3

Content: 285 pages




This is a beginning-level book.

ARM Cache, MMU, and TLB

TLB
TLB maintenance and configuration operations are controlled through CP15 coprocessor. This coprocessor provides a standard mechanism for configuring the level one memory system.

The Cortex-A9 processor implements a 2-level TLB structure. Four entries in the main TLB are lockable.

• Instruction side micro TLB
• Data side micro TLB
• Unified main TLB

Micro TLB: The first level of caching for the page table information is a micro TLB of 32 entries that is implemented on each of the instruction and data sides. These blocks provide a fully associative lookup of the virtual addresses in a single CLK signal cycle. The micro TLB returns the physical address to the cache for the address comparison, and also checks the protection attributes to signal either a Prefetch Abort or a Data Abort.
Main TLB: The main TLB catches the misses from the micro TLBs. It also provides a centralized source for lockable translation entries.

MMU

The MMU works with the L1 and L2 memory system (L1 and L2 Cache) to translate virtual addresses to physical addresses. It also controls accesses to and from external memory.

The Virtual Memory System Architecture version 7 (VMSAv7) features include the following:

• page table entries that support 4KB, 64KB, 1MB, and 16MB
• 16 domains
• global and address space identifiers to remove the requirement for context switch TLB flushes
• extended permissions check capability.

Example: Identity Mapping (Virtual Address = Physical Address)

Init Page Table:

init_pagetable:
    ldr   r2, =0b00000000000000000000110000000010
    ldr   r0, =PAGE_TABLE_ADDR     
    ldr   r1, =0xfff             @ loop 4096
write_descriptor:
    orr   r3, r2, r1, LSL #20             
    str   r3, [r0, r1, LSL #2]            
    subs  r1, r1, #1                      
    bpl   write_descriptor

    /* Set different cacheable attributes */
    @ inner write back, write allocate
    @ set TEX as write back, write allocate
    orr   r3, r2, #1 << 20          
    bic   r3, r3, #0b1100          @ clear CB bits
    orr   r3, r3, #0b0100
    bic   r3, r3, #0b111000000000000 @ clear TEX bits
    orr   r3, r3, #0b101000000000000
    str   r3, [r0, #0x4]

    @ inner non-cacheable
    @ set TEX as write back, write allocate
    orr   r3, r2, #2 << 20          
    bic   r3, r3, #0b1100
    orr   r3, r3, #0b0000
    bic   r3, r3, #0b111000000000000
    orr   r3, r3, #0b101000000000000
    str   r3, [r0, #0x8]

    @ inner write back, write allocate
    @ outer non-cacheable
    orr   r3, r2, #3 << 20          
    bic   r3, r3, #0b1100
    orr   r3, r3, #0b0100
    bic   r3, r3, #0b111000000000000
    orr   r3, r3, #0b100000000000000
    str   r3, [r0, #0xc]

    @ inner non-cacheable
    @ outer non-cacheable
    orr   r3, r2, #4 << 20          
    bic   r3, r3, #0b1100
    orr   r3, r3, #0b0000
    bic   r3, r3, #0b111000000000000
    orr   r3, r3, #0b100000000000000
    str   r3, [r0, #0x10]

Init MMU:

    @ Write Translation Table Base Control Register
    mov   r0, #0x0
    mcr   p15, 0, r0, c2, c0, 2      

    @ Write Translation Table Base Register 0
    ldr   r0, =PAGE_TABLE_ADDR
    mcr   p15, 0, r0, c2, c0, 0           

    @ Write Domain Access Control Register
    @ Set Domains 0 to Client
    mov   r0, #0x01
    mcr   p15, 0, r0, c3, c0, 0

Enable MMU:

    @ Read Control Register configuration data
    mrc   p15, 0, r0, c1, c0, 0           
    orr   r0, r0, #0x1
    mcr   p15, 0, r0, c1, c0, 0

LLVM

LLVM (Low Level Virtual Machine)

Compiler Technology Components
ClooG:
CLooG is a free software and library to generate code for scanning Z-polyhedra. Install CLoog for Polly.

Polly:
Polly is a polyhedral optimizer for LLVM.

Clang:
Clang is to create a new C, C++, Objective C and Objective C++ front-end for the LLVM compiler.

lld:
The LLVM Linker.

LLDB:
LLDB is a high-performance debugger. It is built as a set of reusable components which highly leverage existing libraries in the larger LLVM Project, such as the Clang expression parser and LLVM disassembler.

libcxx:
libc++ is a new implementation of the C++ standard library, targeting C++11.

How to build LLVM on MacBook Air

$ mkdir LLVM
$ cd LLVM
$ wget http://llvm.org/releases/3.4/llvm-3.4.src.tar.gz
$ wget http://llvm.org/releases/3.4/clang-3.4.src.tar.gz
$ wget http://llvm.org/releases/3.4/compiler-rt-3.4.src.tar.gz
$ tar zxf llvm-3.4.src.tar.gz
$ tar zxf clang-3.4.src.tar.gz
$ tar zxf compiler-rt-3.4.src.tar.gz
$ mv clang-3.4/ llvm-3.4/tools/clang/
$ mv compiler-rt-3.4/ llvm-3.4/projects/compiler-rt/

$ mkdir llvm-3.4.build
$ cd llvm-3.4.build
$ ../llvm-3.4/configure --enable-shared
$ time make
 . . . . . . wait . . . . . .

real   88m6.255s

user  82m21.556s

sys   4m25.115s

$ make check-all

Before starting to use LLVM, please remember to include the LLVM binaries in our path.

#(?) Now, you can compile C code by using the clang -- the C front-end for the LLVM compiler.

Intel Bay Trail Atom processor family

Intel

Bay Trail-T

Bay Trail-M

Celeron N2805 (Bay Trail-M), 2 cores @ 1,46 GHz, 4.5W TDP

Celeron N2810 (Bay Trail-M), 2 cores @ 2,00 GHz, 7.5W TDP

Celeron N2910 (Bay Trail-M), 4 cores @ 1,60 GHz, 7.5W TDP

Pentium N3510 (Bay Trail-M), 4 cores @ 2,00 GHz, 7.5W TDP

Bay Trail-D

Celeron J1750 (Bay Trail-D), 2 cores @ 2,41 GHz, 10W TDP

Celeron J1850 (Bay Trail-D), 4 cores @ 2,00 GHz, 10W TDP

Pentium J2850 (Bay Trail-D), 4 cores @ 2,41 GHz, 10W TDP

Bay Trail-I

Atom E3810 (Bay Trail-I), 1 core @ 1,46 GHz, 5W TDP

Atom E3821 (Bay Trail-I), 2 cores @ 1,33 GHz, 6W TDP

Atom E3822 (Bay Trail-I), 2 cores @ 1,46 GHz, 7W TDP

Atom E3823 (Bay Trail-I), 2 cores @ 1,75 GHz, 8W TDP

Atom E3840 (Bay Trail-I), 4 cores @ 1,91 GHz, 10W TDP

Obviously, this new processor family is against ARM.

ARM

Cortex-A

Cortex-M

Cortex-R

Tizen

Tizen is a fresh new project (start from 2011.09). This new ecosystem is for smartphones, tablets, in-vehicle infotainment (IVI) devices, and smart TVs.

We already have Android, why Tizen? Everyone wants to be the boss. :)

Linux Power Management

Bus Blaster

Bus Blaster v2 is an experimental, high-speed JTAG debugger for ARM processors, FPGAs, CPLDs, flash, and more.

http://dangerousprototypes.com/docs/Bus_Blaster

Reference:

HOWTO install OpenOCD in Fedora 14

The way to copy memory on a Cortex-A9

Word by Word memory copy

Load-Multiple memory copy

NEON memory copy

Word by Word memory copy with preload

Load-Multiple memory copy with preload

NEON memory copy with preload


NEONCopyPLD
   PLD [r1, #0xC0]
   VLDM r1!,{d0-d7}
   VSTM r0!,{d0-d7}
   SUBS r2,r2,#0x40 
   BGE NEONCopyPLD


Mixed ARM and NEON memory copy with preload

ARM Community

Web: http://www.arm.com
         http://www.arm.com/community
Blogs: http://blogs.arm.com
twitter: http://twitter.com/ARMCommunity
YouTube: http://youtube.com/ARMflix
Linkedin: http://www.arm.com/Linkedin
Facebook: http://facebook.com/ARMfans

ARM Versatile Express Cortex-A9 (4) Root File System

Buildroot

http://sources.buildroot.net